The invention relates to an image processing apparatus and an image processing method which are suitable for use in realization of a picture-in-picture function or a picture-and-picture function and relates to a television receiver or the like having such an image processing circuit.
In a recent television receiver, a receiver which can perform what is called a picture-in-picture (hereinbelow, referred to as a PinP) to simultaneously display a slave picture plane for an inherent master picture plane or a picture-and-picture (hereinbelow, referred to as a PandP) to simultaneously display two picture planes is being spread. To realize the PinP function or PandP function, an image processing circuit to perform a synchronous crossover or set an image size and a display position is provided in such a kind of television receiver.
The image processing circuit can be constructed by: a field memory; interpolation processing circuits provided at the front and post stages of the field memory; and a memory controller to control the field memory in accordance with the image size and the display position.
That is, in case of reducing the image size, an interpolating process is performed in the interpolation processing circuit at the front stage of the field memory in order to improve a picture quality. An input digital video signal is decimated in accordance with the image size every pixel in the horizontal direction and every line in the vertical direction and the resultant video signal is written into the field memory. The video signal in the field memory is continuously read out.
For example, FIGS. 1A to 1D and 2 show an example in case of reducing an original image of (720 pixelsxc3x97240 lines) to an image of (360 pixelsxc3x97120 lines).
As shown in FIG. 1A, as an original image, sampling image data D00, D01, D02, D03, . . . is inputted in the first one line. In the next (1+1)th line, as shown in FIG. 1C, sampling image data D10, D11, D12, D13, . . . is inputted.
In this case, in the horizontal direction, as shown in FIG. 1B, a write enable signal We is inputted to a field memory every sample and a decimation is performed so as to reduce the number of samples into xc2xd in the horizontal direction. In the vertical direction, the write enable signal We is inputted every line (refer to FIGS. 1B and 1D) and a decimation is performed so as to reduce the number of lines into xc2xd in the vertical direction.
Thus, the data of each sample is decimated with respect to the horizontal direction and the data of each line is decimated with respect to the vertical direction. As shown in FIG. 2, a video signal is written into the field memory in a state where it is reduced into xc2xd.
When the data is continuously read out from the field memory in which the video signal in which the number of samples in the horizontal direction was decimated into xc2xd and the number of lines in the vertical direction was decimated into xc2xd as mentioned above has been stored, the original image of (720 pixelsxc3x97240 lines) can be reduced into the image of (360 pixelsxc3x97120 lines).
In case of magnifying the image size, the input video signal is continuously written into the field memory. The video signal in the field memory is read out in accordance with the image size and a magnifying process by an interpolation is performed at the post stage of the field memory.
As mentioned above, the image processing circuit can be constructed by the field memory, the interpolation processing circuits provided at the front and post stages of the field memory, and the memory controller. However, if it is intended to realize such an image processing circuit by one field memory, there occurs a problem such that the reading position in the field memory overtakes the writing position and a time-dependent discontinuity occurs.
For example, in case of reducing the image size, as mentioned above, the video signal is written into the field memory while decimating the samples and lines of the input video signal and the data is continuously read out from the field memory. In this case, therefore, an address counter on the reading side is incremented faster than an address counter on the writing side.
That is, now assuming that the video signal is written into the field memory on the basis of a line address count signal on the writing side as shown in FIG. 3A, the video signal is read out by a line address count signal as shown in FIG. 3B on the reading side. Since the address counter on the reading side is incremented faster than that on the writing side as mentioned above, as shown in FIG. 3C, when the synchronous crossover and the size switching are simultaneously performed, an overtake occurs at a point (a) where an address count signal on the reading side and an address count signal on the writing side intersect. Present field data is read out for a period of time (b). Past field data is read out for a period of time (c). Thus, a time-dependent discontinuity occurs.
To solve the above problem, as shown in FIG. 4, an apparatus such that two field memories 231 and 232 are provided and the reading and writing operations are alternately performed in the two field memories 231 and 232 every field has been proposed.
In FIG. 4, a memory portion 201 is constructed by the two field memories 231 and 232 and two switching circuits 233 and 234. The writing and reading operations of the two field memories 231 and 232 are switched by the switching circuits 233 and 234.
The switching circuits 233 and 234 equivalently express processes which are eventually performed by performing writing and reading controls to the two field memories 231 and 232.
A writing side memory control circuit 204 and a reading side memory control circuit 205 are provided for the memory portion 201. The writing side memory control circuit 204 controls the field memory serving as a writing side between the field memories 231 and 232. The reading side memory control circuit 205 controls the field memory serving as a reading side between the field memories 231 and 232.
A horizontal/vertical interpolation processing circuit 202 performs an interpolating process so as not to cause a deterioration in picture plane when the image size is reduced. That is, when the image size is reduced, the decimating process is performed in the memory portion 201. If the decimating process is simply performed, however, an aliasing distortion occurs and the picture quality deteriorates. Therefore, the interpolating process is performed in the horizontal/vertical interpolation processing circuit 202 so as not to deteriorate the picture quality. A horizontal/vertical interpolation processing circuit 203 for a magnifying process performs a magnification interpolating process when the image size is magnified. Control information for image processes is supplied to a bus decoder 206 through an internal bus led out from a system controller of the television receiver although not shown. The control information is generated, for example, in accordance with a setting state of a switch or the like on an operation panel of the television receiver.
Image size information (H, VSize) is formed from the bus decoder 206 in accordance with the control information from the system controller. The image size information (H, VSize) is supplied to latch circuits 211 and 212. The image size information (H, VSize) is inputted to the latch circuits 211 and 212 at a timing of a vertical read clock fvr. Outputs of the latch circuits 211 and 212 are supplied to the writing side memory control circuit 204 and reading side memory control circuit 205 and to a magnification/reduction ratio calculating circuit 207.
The magnification/reduction ratio calculating circuit 207 forms interpolation processing information according to its aspect ratio on the basis of the image size information (H, VSize). In case of the reducing process, the interpolation processing information formed in the magnification/reduction ratio calculating circuit 207 is supplied to the horizontal/vertical interpolation processing circuit 202 for the reducing process. In case of the magnifying process, the interpolation processing information formed in the magnification/reduction ratio calculating circuit 207 is supplied to the horizontal/vertical interpolation processing circuit 203 for the magnifying process.
In the writing side memory control circuit 204, the writing side field memory between the field memories 231 and 232 is controlled in accordance with the image size information (H, VSize). Similarly, in the reading side memory control circuit 205, the reading side field memory between the field memories 231 and 232 is controlled in accordance with the image size information (H, VSize).
In case of performing the process to reduce the image size, the image size information (H, VSize) to set a reduced picture plane is outputted from the bus decoder 206. The image size information (H, VSize) to set the reduced picture plane is fetched by the latch circuit 211 at the timing of the vertical read clock fvr, supplied to the writing side memory control circuit 204 and reading side memory control circuit 205, fetched by the latch circuit 212 at the timing of the vertical read clock fvr, and supplied to the magnification/reduction ratio calculating circuit 207. In case of reducing the image size, interpolation processing information for the horizontal/vertical interpolation processing circuit 202 is calculated by the magnification/reduction ratio calculating circuit 207 in accordance with the image size information (H, VSize). The interpolation processing information is set into the horizontal/vertical interpolation processing circuit 202.
A digital video signal is inputted to an input terminal 221. The video signal is supplied to the horizontal/vertical interpolation processing circuit 202. In the horizontal/vertical interpolation processing circuit 202, an interpolating process is performed to prevent the deterioration in picture quality on the basis of the interpolation processing information from the magnification/reduction ratio calculating circuit 207.
The writing and reading operations of the field memories 231 and 232 are switched every field by the switching circuits 233 and 234. An output of the horizontal/vertical interpolation processing circuit 202 is written into the field memory serving as a writing side between the field memories 231 and 232 through the switching circuit 233.
The writing operation to the field memory is controlled by the writing side memory control circuit 204. In case of reducing the image size, the input video signal is decimated by the writing side memory control circuit 204 and written into the field memory 231 or 232. After completion of the writing of the video signal of one field, the switching circuit 233 is switched and the writing side field memory is switched.
The reading operation from the field memory serving as a reading side between the field memories 231 and 232 is controlled by reading side memory control circuit 205. In case of magnifying the image size, the video signal of one field is continuously read out from the field memory serving as a reading side between the field memories 231 and 232. After completion of the reading of the video signal of one field, the switching circuit 234 is switched and the reading side field memory is switched.
An output of the switching circuit 234 is supplied to the horizontal/vertical interpolation processing circuit 203. In case of reducing the image size, the output of the switching circuit 234 is outputted as it is from an output terminal 222 through the horizontal/vertical interpolation processing circuit 203.
The video signal decimated in accordance with the image size is stored into the field memories 231 and 232 and the video signal is continuously read out from the field memories, so that the image of the reduced image size is obtained from the video signal of the output terminal 222.
In case of performing the process to magnify the image size, the image size information (H, VSize) to set a magnified picture plane is outputted from the bus decoder 206. The image size information (H, VSize) to set the magnified picture plane is fetched into the latch circuit 211 at the timing of the vertical read clock fvr, supplied to the writing side memory control circuit 204 and reading side memory control circuit 205, fetched into the latch circuit 212 at the timing of the vertical read clock fvr, and supplied to the magnification/reduction ratio calculating circuit 207. In case of magnifying the image size, the interpolation processing information for the horizontal/vertical interpolation processing circuit 203 is calculated by the magnification/reduction ratio calculating circuit 207 in accordance with the image size information (H, VSize). The interpolation processing information is set into the horizontal/vertical interpolation processing circuit 203.
The digital video signal is inputted to the input terminal 221. The video signal is supplied to the horizontal/vertical interpolation processing circuit 202. In case of magnifying the image size, the video signal from the input terminal 221 is supplied as it is to the switching circuit 233 through the horizontal/vertical interpolation processing circuit 202.
The writing and reading operations of the field memories 231 and 232 are switched by the switching circuits 233 and 234 every field. An output of the horizontal/vertical interpolation processing circuit 202 is written into the field memory serving as a writing side between the field memories 231 and 232 through the switching circuit 233.
The writing operation to the field memory is controlled by the writing side memory control circuit 204. In case of magnifying the image size, the input video signal is continuously written into the field memories 231 and 232. After completion of the writing of the video signal of one field, the switching circuit 233 is switched and the writing side field memory is switched.
The reading operation from the field memory serving as a reading side between the field memories 231 and 232 is controlled by reading side memory control circuit 205. In case of magnifying the image size, the video signal of one field is read out from the field memory serving as a reading side between the field memories 231 and 232 in accordance with the image size. After completion of the reading of the video signal of one field, the switching circuit 234 is switched and the reading side field memory is switched.
The output of the switching circuit 234 is supplied to the horizontal/vertical interpolation processing circuit 203. In case of magnifying the image size, the interpolating process is performed in the horizontal/vertical interpolation processing circuit 203 on the basis of the interpolation processing information from the magnification/reduction ratio calculating circuit 207 in order to magnify and interpolate the picture plane.
The video signal in the field memories is read out in accordance with the image size and the interpolation magnifying process is performed in the horizontal/vertical interpolation processing circuit 203. Thus, the magnified and interpolated image is obtained from the output terminal 222.
As shown in FIG. 4, by providing the two field memories 231 and 232 for the memory portion 201 and switching and using the two field memories 231 and 232, as shown in FIG. 5, the problem such that the reading position overtakes the writing position can be solved by latching a switching signal of the writing side field memory by a vertical read start pulse signal and switching the reading side field memory by the latched signal.
In FIG. 5, a write enable signal is supplied to an input terminal 243. The write enable signal from the input terminal 243 is selectively supplied to the field memories 231 and 232 through a switching circuit 235. The switching circuit 235 is switched by a field switching signal wfsw on the writing side from an input terminal 244. When the write enable signal is inputted to the field memories 231 and 232, data can be written into the field memories 231 and 232.
The writing side field switching signal wfsw and the write enable signal are outputted from the writing side memory control circuit 204 in FIG. 4. The operation to selectively supply the write enable signal to the field memories 231 and 232 by the writing side field switching signal wfsw corresponds to the operation to switch the switching circuit 233 in FIG. 4.
A read enable signal is supplied to an input terminal 245. The read enable signal is selectively supplied to the field memories 231 and 232 through a switching circuit 236. The switching circuit 236 is switched by a field switching signal rfsw on the reading side from a latch circuit 247. When the read enable signal from the input terminal 245 is inputted to the field memories 231 and 232, the data can be read out from the field memories 231 and 232.
The reading side field switching signal rfsw and the read enable signal are outputted from the memory control circuit 205 on the reading side in FIG. 4. The operation to selectively supply the read enable signal to the field memories 231 and 232 by the reading side field switching signal rfsw corresponds to the operation to switch the switching circuit 234 in FIG. 4.
The writing side field switching signal wfsw is supplied to an input terminal 246. The writing side field switching signal wfsw is supplied to the latch circuit 247.
A vertical read start pulse signal rstat is formed in a start position detecting circuit 248 at a vertical read start timing. The vertical read start pulse signal rstat is supplied to the latch circuit 247.
The writing side field switching signal wfsw from the input terminal 246 is latched by the latch circuit 247. An output of the latch circuit 247 is supplied as a reading side field switching signal rfsw to the switching circuit 236.
With respect to the writing process, as shown in FIG. 6A, the field memories 231 and 232 are switched by the writing side field switching signal wfsw. For example, the data is written into the field memory 231 for a field period of time when the writing side field switching signal wfsw is set to the high level. The data is written into the field memory 232 for a field period of time when the writing side field switching signal wfsw is set to the low level.
With regard to the reading process, it is switched by the reading side field switching signal rfsw (FIG. 6C) formed by sampling the writing side field switching signal wfsw (FIG. 6A) by the vertical read start pulse signal rstat (FIG. 6B). For example, the data is read out from the field memory 231 for a field period of time when the reading side field switching signal rfsw is set to the low level. The data is read out from the field memory 232 for a field period of time when the reading side field switching signal rfsw is set to the high level. Therefore, as shown by arrows 91 and 92 in FIGS. 6A to 6D, the data is read out in a state accompanied with a delay of about one field period for the writing process.
As mentioned above, by always controlling such that while the writing process is performed to one of the two field memories, the reading process is performed to the other field memory, the processes for the synchronous crossover and the size change can be performed without causing a situation such that the reading position overtakes the writing position.
In the image processing apparatus in which the countermeasure against the overtaking as mentioned above was taken, however, the image size is changed simultaneously in both of the writing process and the reading process in spite of a fact that the reading timing is delayed from the writing timing by about one field period. Consequently, there occurs a problem such that when the image size is continuously changed, the image size upon writing and that upon reading differ.
For example, now assuming that the image size is changed from (Mxc3x97N) to ((M/2)xc3x97(N/2)) at a timing shown by an arrow 93 in FIG. 6D, at this timing, the new image size information (H, VSize) is set into the writing side memory control circuit 204 and reading side memory control circuit 205 in FIG. 4 at the same timing. Therefore, from this time point, as shown in a hatched region 99 in FIG. 8, the writing operation is performed to the writing side field memory (for example, field memory 231) on the basis of the new image size ((M/2)xc3x97(N/2)). The reading operation is performed to the reading side field memory (for example, field memory 232) on the basis of the new image size ((M/2)xc3x97(N/2)) as shown in a hatched region 97 in FIG. 7.
However, since the image size has been set to (Mxc3x97N) at a timing before such a timing, as shown in a hatched region 98 in FIG. 7, the data of the image size (Mxc3x97N) so far has already been written in the reading side field memory (for example, field memory 232). Therefore, the data of the (Mxc3x97N) pixels is read out as data of the image size of ((M/2)xc3x97(N/2)).
As mentioned above, in the conventional image processing circuit shown in FIG. 4, there is a problem such that when the image size is continuously changed, the image size in the case where the writing was performed and the image size in the case where the reading is performed differ.
It is, therefore, an object of the invention to provide an image processing apparatus, an image processing method, and a television receiver, in which an image size can be continuously smoothly changed in consideration of setting timings of an image size upon writing and an image size upon reading in association with processes which are executed in an image processing apparatus in which a countermeasure against an overtake has been taken.
According to the invention, there is provided an image processing apparatus comprising: a first field memory and a second field memory; writing side memory control means for controlling the operation of a field memory serving as a writing side between the first field memory and the second field memory; reading side memory control means for controlling the operation of a field memory serving as a reading side between the first field memory and the second field memory; and delay means for allowing a delay difference to be provided between a timing of image size information which is set in the writing side memory control means and a timing of image size information which is set in the reading side memory control means in a manner such that an image size when data is written into the first and the second field memories and an image size when the data is read out from the first and the second field memories coincide, characterized in that the image size information is set so that the writing side memory control means and the reading side memory control means have the delay difference, the image size is set by controlling the first field memory and the second field memory by the writing side memory control means and the reading side memory control means in accordance with the image size information, and a switching control of every field is performed in a manner such that while a writing process is performed to one of the field memories, a reading process is performed to the other field memory.
According to the invention, there is provided an image processing method characterized by comprising the steps of: controlling a field memory serving as a writing side between a first field memory and a second field memory by memory control means on the writing side and controlling the field memory serving as a reading side by memory control means on a reading side; allowing a delay difference to be provided between a setting timing of image size information which is set into the writing side memory control means and a setting timing of image size information which is set into the reading side memory control means in a manner such that an image size when data is written into the first and the second field memories and an image size when the data is read out from the first and the second field memories coincide and setting the image size information into the writing side memory control means and the reading side memory control means; setting the image size by controlling the first field memory and the second field memory by the writing side memory control means and the reading side memory control means in accordance with the image size information; and performing a switching control of every field in a manner such that while a writing process is performed to one of the field memories, a reading process is performed to the other field memory.
According to the invention, there is provided a television receiver comprising: first demodulating means for demodulating a first video signal; second demodulating means for demodulating a second video signal; and image processing means for processing the first and/or the second video signal so as to synthesize the first video signal demodulated by the first demodulating means and the second video signal demodulated by the second demodulating means, characterized in that the image processing means is constructed by a first field memory, a second field memory, writing side memory control means for controlling the operation of a field memory serving as a writing side between the first field memory and the second field memory, reading side memory control means for controlling the operation of a field memory serving as a reading side between the first field memory and the second field memory, and delay means for allowing a delay difference to be provided between a timing of image size information which is set in the writing side memory control means and a timing of image size information which is set in the reading side memory control means in a manner such that an image size when data is written into the first and the second field memories and an image size when the data is read out from the first and the second field memories coincide, the image size information is set so that the writing side memory control means and the reading side memory control means have a delay difference, the image size is set by controlling the first field memory and the second field memory by the writing side memory control means and the reading side memory control means in accordance with the image size information, and a switching control of every field is performed in a manner such that while a writing process is performed to one of the field memories, a reading process is performed to the other field memory.
A latch circuit is provided as timing control means for controlling the timing to perform a changing process of the image size. The changing process of the image size is performed on the basis of control information which is supplied through the latch circuit. A timing to change the image size in the reading process is delayed for a timing to change the image size in the writing process in accordance with the delay difference between a writing timing to the field memories and a reading timing therefrom in association with a process of a countermeasure against an overtake.
Therefore, even in the case where sizes and display positions of two picture planes are arbitrarily set and synchronous crossovers are simultaneously performed, an overtake such that the time relation of the data is reversed is not caused when the image data is read out, and even in case of continuously changing the size, the writing image size to the field memories and the reading image size therefrom can be always made coincide, and a smooth display can be performed.